Such a synchronizing circuit is already known in the art, e.g. from the German patent application No 3441501.7 (M. Klein et al 2--2) and may for instance be used for regenerating a high bit-rate digital signal of which the binary or data bit transitions have been subjected to phase shift during their propagation through different electronic circuits.
In this known synchronizing circuit the signal sampling means takes a set of three signal samples of the digital signal in a set of three time positions of this digital signal and provides them simultaneously to the control logic means which performs thereon a logical function which consists in checking whether the three signal samples are equal or not.
As long as the logical function is true, i.e. when the three signal samples are equal, the signal sampling means supply the same medium sample of the set to the one signal sample output used for regenerating the other digital signal. On the other hand, when the logical function is false, i.e. when the three signal samples are not equal, the control logic means operate the signal sampling means in order that the latter should sample the digital signal in another set of three different time positions and should thus provide another medium signal sample to the above one signal sample output. By proceeding in this way one is sure that each binary value or data bit of the digital signal is finally sampled in a region which does not contain a binary or data bit transition.
A drawback of this known synchronizing circuit is that the set of time positions in which the three signal samples have a same value, i.e. for which the logical function is true, is generally located just before or just after a data bit transition. The above phase shift may then jeopardize the synchronization by making this set of time positions to jump from just before/after to just after/before this data bit transition. This negatively affects the bit error rate (BER) of the digital signal which is even worse when the logical function is not performed on every data bit, i.e. on every period of the clock signal, but for instance on every eighth data bit, as may be the case in practice.